CDx4HC4020, CDx4HCT4020 CDHigh-Speed CMOS Logic 14-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge clocking • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range: -55℃ to 125℃ • Balanced propagation delay and transit

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 14STG BINARY COUNTER 16SOIC 集成电路（IC） 计数器，除法器

High-Speed CMOS Logic 14-Stage Binary Counter

文件：269.58 Kbytes Page：13 Pages

High-Speed CMOS Logic 14-Stage Binary Counter

文件：466.11 Kbytes Page：17 Pages

High-Speed CMOS Logic 14-Stage Binary Counter

文件：269.58 Kbytes Page：13 Pages

14-stage binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the “4020” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

14-stage binary ripple counter

1. General description The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all

14-stage binary ripple counter

1. General description The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all

14-stage binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the “4020” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

14-stage binary ripple counter

1. General description The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all