丝印代码：HCT243M；CDx4HC243, CDx4HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs

1 Features • Typical propagation delay (A to B, B to A) of 7ns at VCC = 5 V, CL = 15pF, TA = 25oC • Three-state outputs • Buffered inputs • Fanout (over temperature range) – Standard outputs : 10 LSTTL loads – Bus driver outputs : 15 LSTTL loads • Wide operating temperature range : -55oC t

High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs

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High Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs

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High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs

文件：280.57 Kbytes Page：12 Pages

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

Quad. Bus Transceivers (with 3-state outputs)

Description The HD74HCT242 is an inverting buffer and the HD74HCT243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable (GAB). GBA enables the A outputs and GAB enables the B outputs. The device does not have schmitt trigger inputs. Features • LST