丝印代码：CD74HCT165E；CDx4HC165, CDx4HCT165 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

1 Features • Buffered inputs • Asynchronous parallel load • Complementary outputs • Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads • Wide operating temperature range: -55℃ to 125℃ • Balanced propagation delay and transition times •

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8-bit parallel-in/serial-out shift register

GENERAL DESCRIPTION The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous 8-bit parallel load • Synchronous serial input • Output capability: standard

8 BIT PISO SHIFT REGISTER

DESCRIPTION The M54/74HCT165 is a high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It achives the high speed operation similar to equivalent LSTTL while maintaining