CDx4HCT126 Quadruple Buffers with 3-State Outputs

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC BUF NON-INVERT 5.5V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

High Speed CMOS Logic Quad Buffer, Three-State

文件：36.58 Kbytes Page：7 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：257.85 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

CDx4HCT126 Quadruple Buffers with 3-State Outputs

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

CDx4HCT126 Quadruple Buffers with 3-State Outputs

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：257.85 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC BUF NON-INVERT 5.5V 14SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：831.75 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：257.85 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：444.26 Kbytes Page：14 Pages

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICCcategory: MSI

QUADRUPLE 3-STATE BUFFERS OE HIGH

Description The 74HCT126 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a low logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

Quad buffer/line driver; 3-state

1. General description The 74HC126; 74HCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to i

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICCcategory: MSI

Quad buffer/line driver; 3-state

1. General description The 74HC126; 74HCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to i