High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

高速 CMOS 逻辑 CMOS 可编程的 N 分频计数器

The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number \"N\" from 3 to 15,999. The output signal is a pulse one clock cycle w • Synchronous Programmable N Counter N = 3 to 9999 or 15999\n• Presettable Down-Counter\n• Fully Static Operation\n• Mode-Select Control of Initial Decade Counting Function (10, 8, 5, 4, 2)\n• Master Preset Initialization\n• Latchable N Output\n• Fanout (Over Temperature Range) \n• Standard Outputs ;

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：54.65 Kbytes Page：7 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

丝印代码：HC4059M；High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

丝印代码：HC4059M；High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

Features • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable Down-Counter • Fully Static Operation • Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) • Master Preset Initialization • Latchable ÷N Output • Fanout (Over Temperature Range) - S

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：54.65 Kbytes Page：7 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：209.98 Kbytes Page：12 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：209.98 Kbytes Page：12 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：卷带（TR） 描述：IC COUNTER PROG DIV-BY-N 24-DIP 集成电路（IC） 计数器，除法器

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC COUNTER PROG DIV-BY-N 24-SOIC 集成电路（IC） 计数器，除法器

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：209.98 Kbytes Page：12 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：209.98 Kbytes Page：12 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：381.72 Kbytes Page：14 Pages

High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

文件：352.13 Kbytes Page：14 Pages

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b

Programmable divide-by-n counter

GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the “4059” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency b