CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 12-ST BINARY COUNTER 16SOIC 集成电路（IC） 计数器，除法器

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

CDx4HC4040, CDx4HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter

1 Features • Fully static operation • Buffered inputs • Common reset • Negative edge pulsing • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range... – 55°C to 125°C • Balanced propagation delay and tr

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC 12-ST BINARY COUNTER 16SOIC 集成电路（IC） 计数器，除法器

High-Speed CMOS Logic 12-Stage Binary Counter

文件：346.12 Kbytes Page：15 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

High-Speed CMOS Logic 12-Stage Binary Counter

文件：399.27 Kbytes Page：18 Pages

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

High Speed CMOS Logic

Features  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1μA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage