丝印代码：74HC259；8-bit addressable latch

Features • High speed: tPD = 20 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min.) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tPLH ~= tPHL • Wide operating volta

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

丝印代码：74HC259D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 8-Bit Addressable Latch General The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits ar

丝印代码：74HC259Y；8-bit addressable latch

Features • High speed: tPD = 20 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min.) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tPLH ~= tPHL • Wide operating volta

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

8-bit addressable latch

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

8-bit addressable latch

The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches designed for general-purpose stor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily exp;

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Wide supply voltage range from 2.0 V to 6.0 V\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n• Complies with JEDEC standards:• JESD8C (2.7 V to 3.6 V)\n• JESD7A (2.0 V to 6.0 V)\n\n• Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each s;

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily expandable\n• Common reset input\n• Useful as a 3-to-8 active HIGH decoder\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74H;

8-bit addressable latch

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

8-bit addressable latch

8-bit addressable latch

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

8-bit addressable latch

8-bit addressable latch

8-bit addressable latch

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC ADDRESSABLE LATCH 8BIT 16SOIC 集成电路（IC） 锁存器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 8BIT ADDRESSABLE LATCH 16SOIC 集成电路（IC） 锁存器

8-bit addressable latch

8-bit addressable latch

8-bit addressable latch

8-bit addressable latch

8-Bit Addressable Latch 1-of-8 Decoder

文件：199.53 Kbytes Page：7 Pages

8-Bit Addressable Latch 1-of-8 Decoder

文件：246.95 Kbytes Page：8 Pages