CDx4HC138, CDx4HCT138, CDx4HC238, CDx4HCT238 High-Speed CMOS Logic 3- to 8-Line Decoder/Demultiplexer Inverting and Noninverting

1 Features • Select one of eight data outputs: – Active low for '138 – Active high for '238 • l/O port or memory selector • Three enable inputs to simplify cascading • Typical propagation delay of 13 ns at VCC = 5 V, CL = 15 pF, TA = 25°C • Fanout (over temperature range) – Bus driver out

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

High-Speed CMOS Logic 3- to 8-Line Decoder/Demultiplexer Inverting and Noninverting

文件：765.4 Kbytes Page：19 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：352.78 Kbytes Page：14 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：407.79 Kbytes Page：18 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：360.1 Kbytes Page：15 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：352.78 Kbytes Page：14 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：407.79 Kbytes Page：18 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：360.1 Kbytes Page：15 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：407.79 Kbytes Page：18 Pages

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting

文件：360.1 Kbytes Page：15 Pages

3-to-8 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for mem

3-to-8 line decoder/demultiplexer

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

3-to-8 line decoder/demultiplexer