High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

3-to-8 line decoder, demultiplexer with address latches

1. General description The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decode

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder, demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder, demultiplexer with address latches

3-to-8 line decoder, demultiplexer with address latches