High-Speed CMOS Logic 4-Bit Parallel Access Register

Features • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout

High Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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High-Speed CMOS Logic 4-Bit Parallel Access Register

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4-bit parallel access shift register

GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous master reset • J,K, (D) inputs to the first stage • Fully syn