丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar