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CD74HC11价格
参考价格：￥1.5426
型号：CD74HC112E 品牌：TI 备注：这里有CD74HC11多少钱，2025年最近7天走势，今日出价，今日竞价，CD74HC11批发/采购报价，CD74HC11行情走势销售排行榜，CD74HC11报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD74HC11 | High Speed CMOS Logic Triple 3-Input AND Gate 文件：33.84 Kbytes Page：6 Pages | TI 德州仪器 |   | |
CD74HC11 | High-Speed CMOS Logic Triple 3-Input AND Gate 文件：260.86 Kbytes Page：11 Pages | TI 德州仪器 | | |
CD74HC11 | 3 通道、3 输入、2V 至 6V 与门 | TI 德州仪器 | | |
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
CDx4HC11 Triple 3-Input AND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
具有设置和复位端的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：55.1 Kbytes Page：8 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：55.1 Kbytes Page：8 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI2 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI2 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | |
CD74HC11产品属性
- 类型
描述
- 型号
CD74HC11
- 功能描述
触发器 Dual Neg Edge Trig
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
NA |
20 |
原装正品,假一罚十! |
|||
TI |
20+ |
NA |
53650 |
TI原装主营-可开原型号增税票 |
|||
TI |
20 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||||
HAR |
25+ |
DIP-8P |
18000 |
原厂直接发货进口原装 |
|||
22+ |
5000 |
||||||
TI/德州仪器 |
22+ |
PDIP-14 |
500000 |
原装现货支持实单价优/含税 |
|||
TI |
24+ |
PDIP|16 |
798400 |
免费送样原盒原包现货一手渠道联系 |
|||
TI |
23+ |
18 |
专做原装正品,假一罚百! |
||||
HAR |
24+ |
DIP16 |
48 |
||||
TI |
23+ |
NA |
20000 |
CD74HC11规格书下载地址
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