CD74HC112价格
参考价格：￥1.5426
型号：CD74HC112E 品牌：TI 备注：这里有CD74HC112多少钱，2026年最近7天走势，今日出价，今日竞价，CD74HC112批发/采购报价，CD74HC112行情走势销售排行榜，CD74HC112报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD74HC112 | CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 |   | |
CD74HC112 | 具有设置和复位端的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器 The HC112 and HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Set, Reset, a • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . –55°C to 125°C\n• Significant Pow; | TI 德州仪器 | | |
CD74HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | |
CD74HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：55.1 Kbytes Page：8 Pages | TI 德州仪器 | | |
CD74HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | |
CD74HC112 | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | |
丝印代码：CD74HC112E；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HC112M；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HJ112；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
丝印代码：HJ112；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：55.1 Kbytes Page：8 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：765.86 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：757.59 Kbytes Page：20 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：346.89 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：643.79 Kbytes Page：18 Pages | TI 德州仪器 | |
CD74HC112产品属性
- 类型
描述
- Technology Family：
HC
- Supply voltage (Min) (V)：
2
- Supply voltage (Max) (V)：
6
- Input type：
LVTTL/CMOS
- Output type：
Push-Pull
- Clock Frequency (MHz)：
24
- ICC (Max) (uA)：
40
- IOL (Max) (mA)：
6
- IOH (Max) (mA)：
-6
- Features：
Balanced outputs
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
20+ |
SOIC |
53650 |
TI原装主营-可开原型号增税票 |
|||
TI |
2025+ |
TSSOP16 |
3785 |
全新原厂原装产品、公司现货销售 |
|||
TI |
23+ |
16-TSSOP |
65600 |
||||
TI |
23+ |
18 |
专做原装正品,假一罚百! |
||||
TI |
07+ |
SOP3.9MM |
43 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
TI |
24+ |
TSSOP-16 |
25000 |
一级专营品牌全新原装热卖 |
|||
TI/德州仪器 |
25+ |
PDIP16 |
20000 |
原装 |
|||
TI/TEXAS |
26+ |
SOIC16 |
8931 |
代理全系列销售, 全新原装正品,价格优势,长期供应,量大可订 |
|||
TI(德州仪器) |
23+ |
TSSOP-16 |
13650 |
公司只做原装正品,假一赔十 |
|||
TI/德州仪器 |
23+ |
PDIP16 |
5000 |
只有原装,欢迎来电咨询! |
CD74HC112规格书下载地址
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DdatasheetPDF页码索引
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