CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

Dual JK Positive Edge-Triggered Flip-Flop

General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti

Dual JK Positive Edge-Triggered Flip-Flop

General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti

Dual JK Positive Edge-Triggered Flip-Flop

文件：339.62 Kbytes Page：12 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：339.62 Kbytes Page：12 Pages