High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：286.35 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：282.94 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：288.18 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：288.18 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：282.94 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：286.35 Kbytes Page：14 Pages

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING

DESCRIPTION The M54/74HC373/533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. The application designer has a choise of