Octal Transparent Latch Three-State, Non-Inverting

Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl

CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

1 Features • SCR-Latchup-resistant CMOS process and circuit design • Speed of bipolar FAST*/AS/S with significantly reduced power consumption • Balanced propagation delays • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply • ±24mA output drive cu

Octal Transparent Latch Three-State, Non-Inverting

Description\nThe CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable

具有三态输出的八路透明锁存器

The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\\) is HIGH. When the Latch Enable (LE\\) goes LOW, the data is latched. The Output • Buffered inputs\n• Typical pro-agation delay: 4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF\n• Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015\n• SCR-Latchup-resistant CMOS process and circuit design\n• Speed of bipolar FAST*/AS/S with significantly reduced power consumption\n• Balanced propaga;

Octal Transparent Latch

文件：1.26556 Mbytes Page：17 Pages

OCTAL TRANSPARENT LATCH, 3-STATE

文件：233.95 Kbytes Page：8 Pages

Octal Transparent Latch Three-State, Non-Inverting

Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl

CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

1 Features • SCR-Latchup-resistant CMOS process and circuit design • Speed of bipolar FAST*/AS/S with significantly reduced power consumption • Balanced propagation delays • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply • ±24mA output drive cu

CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

1 Features • SCR-Latchup-resistant CMOS process and circuit design • Speed of bipolar FAST*/AS/S with significantly reduced power consumption • Balanced propagation delays • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply • ±24mA output drive cu

Octal Transparent Latch

文件：1.26556 Mbytes Page：17 Pages

Octal Transparent Latch Three-State, Non-Inverting

Octal Transparent Latch with TRI-STATE Outputs

文件：166.1 Kbytes Page：10 Pages

Octal Transparent Latch with TRI-STATE Outputs

文件：166.1 Kbytes Page：10 Pages

Octal Transparent Latch with TRI-STATE Outputs

文件：166.1 Kbytes Page：10 Pages

Octal Transparent Latch with TRI-STATE Outputs

文件：166.1 Kbytes Page：10 Pages

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

文件：99.83 Kbytes Page：6 Pages