Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

具有设置和复位端的双路负边沿触发式 J-K 触发器

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the J and K inputs meeting the setu • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage\n• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n• Balanced Propagation Delays\n• ±24-mA Output Drive Current \n• Fanout to 15 F Devices\n \n• SCR-Latchup-Resistant;

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：331.08 Kbytes Page：6 Pages

Dual j-k Flip-Flop with Set and Reset

文件：228.31 Kbytes Page：8 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：336.12 Kbytes Page：11 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

文件：903.12 Kbytes Page：15 Pages

丝印代码：CD54AC112F3A；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

丝印代码：CD54AC112F3A；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：336.12 Kbytes Page：11 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

文件：903.12 Kbytes Page：15 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

文件：903.12 Kbytes Page：15 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：336.12 Kbytes Page：11 Pages

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：331.08 Kbytes Page：6 Pages

Dual J-K Flip-Flop with Set and Reset