Dual J-K Flip-Flop with Set and Reset

Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi

CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

具有设置和复位端的双路正边沿触发式 J-K 触发器

The ’AC109 devices contain two independent J-K\\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the J and K\\ inputs meeting the • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage\n• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n• Balanced Propagation Delays\n• ±24-mA Output Drive Current \n• Fanout to 15 F Devices\n \n• SCR-Latchup-Resistant;

Dual j-k Flip-Flop with Set and Reset

文件：228.31 Kbytes Page：8 Pages

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：541.62 Kbytes Page：15 Pages

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：346.39 Kbytes Page：12 Pages

丝印代码：CD54AC109F3A；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

丝印代码：CD54AC109F3A；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：541.62 Kbytes Page：15 Pages

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：541.62 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Set and Reset

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：346.39 Kbytes Page：12 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages