CMOS Dual 64-Stage Static Shift Register

Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted

CMOS DUAL 64-STAGE STATIC SHIFT REGISTER

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CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

Cmos Dual 64-stage Static Shift Register

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CMOS Dual 64-Stage Static Shift Register

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Dual 64-bit Static Shift Register

Dual 64−Bit Static Shift Register

Dual 64-Bit Static Shift Register