丝印代码：CD4035BF；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

丝印代码：CD4035BF；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

CMOS 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

文件：269.47 Kbytes Page：6 Pages

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes Page：17 Pages

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes Page：16 Pages

丝印代码：8101701EA；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

丝印代码：8101701EA；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes Page：17 Pages

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes Page：16 Pages

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

POWER TRANSISTORS(16A,60-100V,150W)

MEDIUM-POWER COMPLEMENTARY SILICON TRANSISTORS designed for use as output devices in complementary general purpose amplifier applications. FEATURES: * High Gain Darlington Performance * DCCurrent Gain hFE = 3500(Typ) @ lc = 10A * Monolithic Construction with Built-in Base-Emitter Shunt Res

CMOS 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

CMOS 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

4-bit universal shift register

4-bit universal shift register

4-bit universal shift register