丝印代码：CD4029BF；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input