CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

CMOS 可预置加/减计数器

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\\ (CLOCK ENABLE\\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT • Medium-speed operation… 8 MHz (typ.) @ CL = 50 pF and VDD–VSS = 10 V\n• \"Preset Enable\" and individual \"Jam\" inputs provided\n• BCD outputs in decade mode\n• 5-V, 10-V, and 15-V parametric ratings\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and ;

CMOS PRESETTABLE UP/DOWN COUNTER

文件：1.03602 Mbytes Page：18 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes Page：8 Pages

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input