CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes Page：12 Pages

CMOS Dual J-K Master-Slave Flip-Flop

文件：676.57 Kbytes Page：14 Pages

CMOS Dual J-K Master-Slave Flip-Flop

文件：1.51688 Mbytes Page：27 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes Page：12 Pages

CMOS Dual J-K Master-Slave Flip-Flop

文件：676.57 Kbytes Page：14 Pages

CMOS Dual J-K Master-Slave Flip-Flop

文件：676.57 Kbytes Page：14 Pages

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V