4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

CMOS 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

文件：233.64 Kbytes Page：7 Pages

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

CMOS 4-Bit Bidirectional Universal Shift Register

文件：342.33 Kbytes Page：9 Pages

4-bit Bidirectional Universal Shift Register

4-Bit Bidirectional Universal Shift Register

4-Bit Bidirectional Universal Shift Register