丝印代码：CD40160BF3A；CMOS Synchronous Programmable 4-Bit Counters

Features: Internal look-ahead for fast counting Carry output for cascading Synchronously programmable Clear asynchronous input {CD40160B, CD40161B) Clear synchronous input (CD40162B, CD40163B) Synchronous load control input Bm Low-power TTL compatibility m Standardized, symmetrical

丝印代码：CD40160BF3A；CMOS Synchronous Programmable 4-Bit Counters

Features: Internal look-ahead for fast counting Carry output for cascading Synchronously programmable Clear asynchronous input {CD40160B, CD40161B) Clear synchronous input (CD40162B, CD40163B) Synchronous load control input Bm Low-power TTL compatibility m Standardized, symmetrical

CMOS Synchronous Programmable 4-Bit Counters

文件：552.41 Kbytes Page：13 Pages

CMOS Synchronous Programmable 4-Bit Counters

文件：958.23 Kbytes Page：17 Pages

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

文件：310.5 Kbytes Page：15 Pages

Decade Counter with Asynchronous Clear

Decade Counter with Asynchronous Clear

Decade Counter with Asynchronous Clear

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

4-bit synchronous decade counter with asynchronous reset

4-bit synchronous decade counter with asynchronous reset

4-bit synchronous decade counter with asynchronous reset

C2MOS DIGITAL INTERGRATED CIRCUIT SILICON MONOLITHIC