CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

CMOS 8-Stage Presettable Synchronous Down Counters

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

Inductive Sensor

Features ■M12 × 1 threaded barrel ■Chrome-plated brass ■DC 2-wire, nom. 8.2 VDC ■Output acc. to DIN EN 60947-5-6 (NAMUR) ■M12 x 1 male connector ■ATEX category II 1 G, Ex zone 0 ■ATEX category II 1 D, Ex zone 20 ■SIL2 (Low Demand Mode) acc. to IEC 61508, PL c acc. to ISO 13849-1 with HFT0