丝印代码：CD40102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CD40102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8 级可预置 2 位十进制 BCD 同步递减计数器

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enablin • Synchronous or asynchronous preset\n• Cascadable\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Standardized, symmetrical output characteristics\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for De;

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

丝印代码：CD40102BE；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CD40102BE；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Description\nCD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has contr • High Voltage Type (20V Rating)\n• CD40102BMS: 2-Decade BCD Type\n• CD40103BMS: 8-Bit Binary Type\n• Synchronous or Asynchronous Preset\n• Medium Speed Operation\n   - fCL = 3.6MHz (Typ) at 10V\n• Cascadable\n• 100% Tested for Quiescent Current at 20V\n• Maximum Input Current of 1µA at 18V Over;

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SYNC DOWN COUNTER 8STG 16SO 集成电路（IC） 计数器，除法器

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC SYNC DOWN COUNTR 8STG 16TSSOP 集成电路（IC） 计数器，除法器

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes Page：17 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes Page：14 Pages

8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

DESCRIPTION The HCC40102B, HCC40103B, (extended temperature range) and the HCF40102B, HCF40103B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF40102B, and HCC/HCF40103B consist of an 8-stage synchronous