CMOS 18-Stage Static Register

Features • High-Voltage Type (20V Rating) • Fully Static Operation • Shifting Rates Up to 12MHz at 10V (typ) • Permanent Register Storage with Clock Line High or Low - No Information Recirculation Required • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Cha

丝印代码：CD4006BF3A；CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

丝印代码：CD4006BF3A；CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

18-Stage Static Shift Register

General Description\nThe CD4006BM/CD4006BC 18-stage static shift register is comprised of four separate shift register sections, two sections of four stages and two sections of five stages. Each section has an independent data input. Outputs are available at the fourth stage and the fifth stage of e ■ Wide supply voltage range 3.0V to 15V\n■ High noise immunity 0.45 VDD (typ.)\n■ Low power TTL fan out of 2 driving 74L\n   compatibility or 1 driving 74LS\n■ Low clock input capacitance 6 pF (typ.)\n■ Medium speed 10 MHz (typ.) (with VDD e 10V)\n■ Low power\n■ Fully static operation;

CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

CMOS 18-Stage Static Register

Description CD4006BMS types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path. A common clock signal is used for all stages. Data are shifte

CMOS 18-STAGE STATIC SHIFT REGISTER

文件：217.08 Kbytes Page：5 Pages

CMOS 18-Stage Static Shift Register

文件：368.18 Kbytes Page：8 Pages

18-Stage Static Shift Register

18-Stage Static Shift Register

文件：112.68 Kbytes Page：6 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：(N) 18 STAGE SHIFT REGISTER 集成电路（IC） 移位寄存器

(N) 18 STAGE SHIFT REGISTER

CMOS 18-Stage Static Shift Register

文件：368.18 Kbytes Page：8 Pages

CMOS 18-Stage Static Shift Register

文件：368.18 Kbytes Page：8 Pages

18-Stage Static Shift Register

文件：112.68 Kbytes Page：6 Pages

CMOS 18-Stage Static Shift Register

文件：368.18 Kbytes Page：8 Pages

18-stage static shift register

DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two 5-stage shift registers each have a data input (DC,

18-stage static shift register

DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two 5-stage shift registers each have a data input (DC,

18-stage static shift register

DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two 5-stage shift registers each have a data input (DC,

18-stage static shift register

DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two 5-stage shift registers each have a data input (DC,

GLASS PASSIVATED JUNCTION PLASTIC RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 1.0 Ampere)

FEATURES ● Plastic package has Underwriters Laboratory Flammability Classification 94V-O utilizing Flame Retardant Epoxy Molding Compound ● Glass passivated junction version of PG4001S thru PG4007S in A-405 package ● 1 ampere operation at TA=75 ¢J with no thermal runaway ● Exceeds environmenta

18-STAGE STATIC SHIFT REGISTER

18-bit Static Shift Register

18-stage static shift register

18-stage static shift register

18-stage static shift register

COMPLEMENTARY METAL OXIDE SILICON