丝印代码：C3BR；SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs

1 Features 1• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • Available in Texas Instruments NanoStar™ and NanoFree™ Packages • Supports 5-V

丝印代码：C3BR；Dual 2-Input NAND Gate With Schmitt-Trigger Inputs

1FEATURES 2• Available in Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Max tpd of 5.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground Bounce)

丝印代码：C3BR；SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs

1 Features 1• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • Available in Texas Instruments NanoStar™ and NanoFree™ Packages • Supports 5-V

丝印代码：C3BR；Dual 2-Input NAND Gate With Schmitt-Trigger Inputs

文件：1.03491 Mbytes Page：20 Pages

丝印代码：C3BR；Dual 2-Input NAND Gate With Schmitt-Trigger Inputs

文件：1.03491 Mbytes Page：20 Pages

丝印代码：C3BR；Dual 2-Input NAND Gate With Schmitt-Trigger Inputs

文件：1.03491 Mbytes Page：20 Pages