位置:LP62S16128BU-55LLT > LP62S16128BU-55LLT详情

LP62S16128BU-55LLT中文资料

厂家型号

LP62S16128BU-55LLT

文件大小

160.05Kbytes

页面数量

14

功能描述

128K X 16 BIT LOW VOLTAGE CMOS SRAM

数据手册

下载地址一下载地址二

生产厂商

AMICC

LP62S16128BU-55LLT数据手册规格书PDF详情

General Description

The LP62S16128B-T is a low operating current 2,097,152-bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 2.7V to 3.6V. It is built using AMICs high performance CMOS process.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing.

Data retention is guaranteed at a power supply voltage as low as 2V.

Features

■ Operating voltage: 2.7V to 3.6V

■ Access times: 55/70 ns (max.)

■ Current:

Very low power version: Operating: 55ns 40mA (max.)

70ns 35mA (max.)

Standby: 10mA (max.)

■ Full static operation, no clock or refreshing required

■ All inputs and outputs are directly TTL-compatible

■ Common I/O using three-state output

■ Data retention voltage: 2V (min.)

■ Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm) packages

LP62S16128BU-55LLT产品属性

  • 类型

    描述

  • 型号

    LP62S16128BU-55LLT

  • 制造商

    AMICC

  • 制造商全称

    AMIC Technology

  • 功能描述

    128K X 16 BIT LOW VOLTAGE CMOS SRAM

更新时间:2025-10-7 17:06:00
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