General Description

The A49LF040A flash memory device is designed to be read-compatible with the Intel Low Pin Count (LPC) Interface Specification 1.1. This device is designed to use a single low voltage, range from 3.0 Volt to 3.6 Volt power supply to perform in-system or off-system read and write operations. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general-purpose inputs. Two interface modes are supported by the A49LF040A: Low Pin Count (LPC) Interface mode for In-System programming and Address/Address Multiplexed (A/A Mux) mode for fast factory programming of PC-BIOS applications.

FEATURES

• Single Power Supply Operation

- Low voltage range: 3.0 V - 3.6 V for Read and Write Operations

• Standard Intel Low Pin Count Interface

- Read compatible to Intel® Low Pin Count (LPC) interface

• Memory Configuration

- 512K x 8 (4 Mbit)

• Block Architecture

- 4Mbit: eight uniform 64KByte blocks

- Supports full chip erase for Address/Address Multiplexed (A/A Mux) mode

• Automatic Erase and Program Operation

- Embedded Byte Program and Block/Chip Erase algorithms

- Typical 10 µs/byte programming time

- Typical 1s block erase time

• Two Operational Modes

- Low Pin Count Interface (LPC) Mode for in-system operation

- Address/Address Multiplexed (A/A Mux) Interface Mode for programming equipment

• Low Pin Count (LPC) Mode

- 33 MHz synchronous operation with PCI bus

- 5-signal communication interface for in-system read and write operations

- Standard SDP Command Set

- Data Polling (I/O7) and Toggle Bit (I/O6) features

- Block Locking Register for all blocks

- 4 ID pins for multi-chip selection

- 5 GPI pins for General Purpose Input Register

- TBL pin for hardware write protection to Boot Block

- WP pin for hardware write protection to whole memory array except Boot Block

• Address/Address Multiplexed (A/A Mux) Mode

- 11-pin multiplexed address and 8-pin data I/O interface

- Supports fast programming on EPROM programmers

- Standard SDP Command Set

- Data Polling (I/O7) and Toggle Bit (I/O6) features

• Lower Power Consumption

- Typical 12mA active read current

- Typical 24mA program/erase current

• High Product Endurance

- Guarantee 100,000 program/erase cycles for each block

- Minimum 20 years data retention

• Compatible Pin-out and Packaging

- 32-pin (8 mm x 14 mm) TSOP (TYPE I)

- 32-pin PLCC

- Optional Pb-free (Lead-free) package

- All Pb-free (Lead-free) products are RoHS compliant