2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

Very Low Noise, 24-Bit Analog-to-Digital Converter

FEATURES 24 Bits, No Missing Codes − All Data Rates and PGA Settings Up to 23 Bits Noise-Free Resolution ±0.0010% Nonlinearity (max) Data Output Rates to 30kSPS Fast Channel Cycling − 18.6 Bits Noise-Free (21.3 Effective Bits) at 1.45kHz One-Shot Conversions with Single-Cycle Settlin

Original Strain Relief Bushings

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Protects USB VBus operating up to 12V

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Very Low Noise, 24-Bit Analog-to-Digital Converter

文件：427.07 Kbytes Page：39 Pages

Very Low Noise, 24-Bit Analog-to-Digital Converter

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