18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge