LIN Bus Transceiver with Integrated Voltage Regulator

Description ATA6620N is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems.

LIN Bus Transceiver with Integrated Voltage Regulator

文件：383.45 Kbytes Page：22 Pages

LIN Bus Transceiver with Integrated Voltage Regulator

LIN Bus Transceiver with Integrated Voltage Regulator

Description ATA6620N is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems.

LIN Bus Transceiver with Integrated Voltage Regulator

文件：383.45 Kbytes Page：22 Pages

LIN Bus Transceiver with Integrated Voltage Regulator

文件：383.45 Kbytes Page：22 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC TRANSCEIVER HALF 1/1 8SO 集成电路（IC） 驱动器，接收器，收发器

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

文件：399.31 Kbytes Page：44 Pages