3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K × 18 pipeline burst synchronous SRAM

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control

3.3V 128K x 18 pipeline burst synchronous SRAM

Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control