3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

封装/外壳：44-TSOP（0.400"，10.16mm 宽） 包装：管件 描述：IC SRAM 1MBIT PARALLEL 44TSOP2 集成电路（IC） 存储器

3.3 V 64K x 16 CMOS SRAM

封装/外壳：44-TSOP（0.400"，10.16mm 宽） 包装：管件 描述：IC SRAM 1MBIT PARALLEL 44TSOP2 集成电路（IC） 存储器

3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

3.3 V 64K X 16 CMOS SRAM

Functional description The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and