5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

封装/外壳：32-TFSOP（0.724"，18.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SRAM 1MBIT PARALLEL 32TSOP I 集成电路（IC） 存储器

封装/外壳：32-TFSOP（0.724"，18.40mm 宽） 包装：卷带（TR） 描述：IC SRAM 1MBIT PARALLEL 32TSOP I 集成电路（IC） 存储器

5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and

5V 128K X 8 CMOS SRAM

Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and