10G USB 3.2 Re-timer (1-Port)

Features * Built-in re-timer ㅡ Integrated re-timer for USB 3.2 1-port (Tx/Rx) up to 10Gbps ㅡ Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re- * timer (BLR) Architectures of USB3.1 Specification (Appendix-E) ㅡ 1055 compensation to recover up to 23dB channel loss

Bidirectional Active USB-C™ Cable for USB3.2 (10G) and DP1.3 (8.1G)

Features  Bidirectional active USB-C cable carrying 4L DP or 2L DP and USB3.2 - Supports up to 4L of DisplayPort in/out, with signal conditioning up to 8.1Gbps (supports HBR3, HBR2, HBR, RBR rates) - Supports USB3.1 in/out, with signal conditioning up to 10Gbps - Supports USB2.0 (480Mbps) -

8.1G (up to HBR3) DisplayPort™ 4-lane Re-timer

Features  Built-in re-timers − Integrated re-timers (Link training-tunable PHY repeater) for DisplayPort up to HBR3 @ 8.1Gbps. Supports both transparent mode and non-transparent mode (transparent or LTTPR) − Loss compensation to recover up to 27dB  Integrated AUX pass-through − Integrated A

6G Active Re-driver with Linear Equalization for HDMI 2.0

Features • Built-in Re-driver with CTLE − Integrated Re-driver for HDMI2.0 up to 6Gbps − Supports DP++, HDMI Source applications − Loss compensation to recover up to -10dB channel loss @6Gbps • CTLE, Flat Gain and Swing configurations − Four-lane configurations set by pin strapping. − Indep

10G Active Redriver with Linear Equalization for USB3.2/DisplayPort™

Features • Built-in redrivers − Integrated re-driver for USB3.2 up to Gen 2 @ 10Gbps − Integrated re-drivers for DisplayPort up to UHBR10 @ 10Gbps. − Supports both host (source) and device (sink) applications in USB-C subsystems with DisplayPort Alternate Mode − Loss compensation to recover u

12G Active Redriver with Linear Equalization for HDMI 2.1

Features  Built-in CTLE redrivers - Independent channel configuration - Loss compensation to recover up to -12dB channel loss @ 12Gbps  Four lanes of HDMI 2.1 up to 12Gbps - Supports DP++  Serial and debug interfaces - I2C Slave interface, up to 1MHz, for redriver configuration  Indust

10G Active Mux (4x4) with Integrated Re-timers for USB3.2/DisplayPort™

Features  Built-in re-timers − Integrated re-timers for USB3.2 up to Gen 2 @ 10Gbps − US3.2 Specification (Appendix-E) compliant re-timer − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB3.2 Specification (Appendix-E) − Integrat

106 Active Mux (6x4) with Integrated Re-timers for USB3.2/DisplayPort1.4

Features * Built-in re-timers — Integrated re-timers for USB3.2 up to Gen 2 @ 10Gbps — Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB3.2 Specification (Appendix-E) — Integrated re-timers (Link training-tunable PHY repeater) for D

20G Active Mux (2x2) with Integrated Re-timer and CC Detection for USB 3.2

Features  Built-in re-timer − Integrated re-timer for USB 3.2 up to Gen 2 @ 2x10Gbps for a combined 20G data throughput − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification (Appendix-E) − Supports both host (source

10G Active Mux (1x2) with Integrated Re-timer and CC Detection for USB 3.2

Features  Built-in re-timer − Integrated re-timer for USB 3.2 up to Gen2 @ 10Gbps − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification (Appendix-E) − Loss compensation to recover up to 23dB channel loss  Integrat

20G Active Retimer for USB 3.2

Features  Built-in re-timer - Integrated re-timer for USB 3.2 with two lanes up to Gen2 @ 10Gbps each for a combined 20G throughput - Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification - Supports both host (source)

10G Active Mux (1x2) with Integrated Re-timer for USB 3.2

Features * Built-in re-timer ㅡ Integrated re-timer for USB 3.2 up to Gen2 @ 10Gbps — Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification (Appendix-E) — Supports both host (source) and device (sink) applications in US

HEXFET Power MOSFET

Benefits ● Low Gate to Drain Charge to Reduce Switching Losses ● Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) ● Fully Characterized Avalanche Voltage and Current Applications ● High frequency DC-DC converters

Bipolar Transistor -50V, -0.4A, Low VCE(sat) PNP Single SSFP

Bipolar Transistor –50V, –0.4A, Low VCE(sat) PNP Single SSFP Features • Large current capacity • Low collector-to-emitter saturation voltage (resistance) : RCE(sat) typ=210mΩ[IC=0.5A, IB=50mA] • Ultrasmall package facilitates miniaturization in end products • Small ON-resistance (Ron) Appli

HEXFET Power MOSFET

Benefits ● Low Gate to Drain Charge to Reduce Switching Losses ● Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) ● Fully Characterized Avalanche Voltage and Current Applications ● High frequency DC-DC converters ● Lead-Free