10GUSB3.2Re-timer(1-Port)

Features *Built-inre-timer ㅡIntegratedre-timerforUSB3.21-port(Tx/Rx)upto10Gbps ㅡSupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe- *timer(BLR)ArchitecturesofUSB3.1Specification(Appendix-E) ㅡ1055compensationtorecoverupto23dBchannelloss

10GActiveRedriverwithLinearEqualizationforUSB3.2/DisplayPort™

Features •Built-inredrivers −Integratedre-driverforUSB3.2uptoGen2@10Gbps −Integratedre-driversforDisplayPortuptoUHBR10@10Gbps. −Supportsbothhost(source)anddevice(sink)applicationsinUSB-CsubsystemswithDisplayPortAlternateMode −Losscompensationtorecoveru

6GActiveRe-driverwithLinearEqualizationforHDMI2.0

Features •Built-inRe-driverwithCTLE −IntegratedRe-driverforHDMI2.0upto6Gbps −SupportsDP++,HDMISourceapplications −Losscompensationtorecoverupto-10dBchannelloss@6Gbps •CTLE,FlatGainandSwingconfigurations −Four-laneconfigurationssetbypinstrapping. −Indep

8.1G(uptoHBR3)DisplayPort™4-laneRe-timer

Features Built-inre-timers −Integratedre-timers(Linktraining-tunablePHYrepeater)forDisplayPortuptoHBR3@8.1Gbps.Supportsbothtransparentmodeandnon-transparentmode(transparentorLTTPR) −Losscompensationtorecoverupto27dB IntegratedAUXpass-through −IntegratedA

BidirectionalActiveUSB-C™CableforUSB3.2(10G)andDP1.3(8.1G)

Features BidirectionalactiveUSB-Ccablecarrying4LDPor2LDPandUSB3.2 -Supportsupto4LofDisplayPortin/out,withsignalconditioningupto8.1Gbps(supportsHBR3,HBR2,HBR,RBRrates) -SupportsUSB3.1in/out,withsignalconditioningupto10Gbps -SupportsUSB2.0(480Mbps) -

12GActiveRedriverwithLinearEqualizationforHDMI2.1

Features Built-inCTLEredrivers -Independentchannelconfiguration -Losscompensationtorecoverupto-12dBchannelloss@12Gbps FourlanesofHDMI2.1upto12Gbps -SupportsDP++ Serialanddebuginterfaces -I2CSlaveinterface,upto1MHz,forredriverconfiguration Indust

10GActiveMux(4x4)withIntegratedRe-timersforUSB3.2/DisplayPort™

Features Built-inre-timers −Integratedre-timersforUSB3.2uptoGen2@10Gbps −US3.2Specification(Appendix-E)compliantre-timer −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Integrat

106ActiveMux(6x4)withIntegratedRe-timersforUSB3.2/DisplayPort1.4

Features *Built-inre-timers —Integratedre-timersforUSB3.2uptoGen2@10Gbps —SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) —Integratedre-timers(Linktraining-tunablePHYrepeater)forD

20GActiveRetimerforUSB3.2

Features Built-inre-timer -Integratedre-timerforUSB3.2withtwolanesuptoGen2@10Gbpseachforacombined20Gthroughput -SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification -Supportsbothhost(source)

10GActiveMux(1x2)withIntegratedRe-timerforUSB3.2

Features *Built-inre-timer ㅡIntegratedre-timerforUSB3.2uptoGen2@10Gbps —SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) —Supportsbothhost(source)anddevice(sink)applicationsinUS

20GActiveMux(2x2)withIntegratedRe-timerandCCDetectionforUSB3.2

Features Built-inre-timer −Integratedre-timerforUSB3.2uptoGen2@2x10Gbpsforacombined20Gdatathroughput −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Supportsbothhost(source

Quad2-InputORGate

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P-Channel30-VMOSFET

文件：393.45 Kbytes Page：7 Pages

P-Channel30-V(D-S)MOSFET

文件：79.27 Kbytes Page：3 Pages