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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ADSP-21591 | SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 |   | |
ADSP-21591 | SHARC Dual-Core DSP with Arm Cortex-A5 文件：3.26181 Mbytes Page：143 Pages | AD 亚德诺 | | |
ADSP-21591 | 800 MHz双核SHARC+® DSP（带2个640KB L1）、1024KB共用的L2 SRAM、400引脚FCBGA封装 | AD 亚德诺 | | |
SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 文件：3.26181 Mbytes Page：143 Pages | AD 亚德诺 | | ||
封装/外壳：400-FBGA 包装：托盘 描述：2 X 800MHZ SHARC+ 集成电路（IC） DSP（数字信号处理器） | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 文件：3.26181 Mbytes Page：143 Pages | AD 亚德诺 | | ||
SHARC Dual-Core DSP with Arm Cortex-A5 文件：3.26181 Mbytes Page：143 Pages | AD 亚德诺 | | ||
DIMMING BALLAST CONTROL IC Description The IR2159/IR21591 are complete dimming ballast controllers and 600V half-bridge drivers all in one IC. The architecture includes phase control for transformer-less lamp power sensing and regulation which minimizes changes needed to adapt non-dimming ballasts for dimming. Featu | IRF | | ||
DIMMING BALLAST CONTROL IC Description The IR2159/IR21591 are complete dimming ballast controllers and 600V half-bridge drivers all in one IC. The architecture includes phase control for transformer-less lamp power sensing and regulation which minimizes changes needed to adapt non-dimming ballasts for dimming. Featu | IRF | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ADI/亚德诺 |
2450+ |
CSPBGA-400 |
9850 |
只做原厂原装正品现货或订货假一赔十! |
|||
ADI(亚德诺)/LINEAR(凌特) |
20+ |
BGA-400 |
20000 |
||||
ADI |
24+ |
400-Ball BGA_ED (17mm x 17mm x |
3660 |
十年信誉,只做全新原装正品现货,以优势说话 !! |
|||
ADI |
23+ |
BGA |
3600 |
绝对全新原装!现货!特价!请放心订购! |
|||
ADI/亚德诺 |
2511 |
原封装 |
66900 |
电子元器件采购降本30%!原厂直采,砍掉中间差价 |
|||
ADI/亚德诺 |
23+ |
TRAY |
3000 |
只做原装正品,假一赔十 |
|||
ADI/亚德诺 |
25+ |
原厂封装 |
10280 |
原厂授权代理,专注军工、汽车、医疗、工业、新能源！ |
|||
ADI(亚德诺) |
25+ |
BGA-400 |
500000 |
源自原厂成本,高价回收工厂呆滞 |
|||
ADI(亚德诺) |
24+ |
BGA-400 |
907 |
深耕行业12年,可提供技术支持。 |
|||
ADI/亚德诺 |
25+ |
20000 |
原装现货,可追溯原厂渠道 |
ADSP-21591芯片相关品牌
ADSP-21591规格书下载地址
ADSP-21591参数引脚图相关
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DdatasheetPDF页码索引
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