1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

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封装/外壳：24-WFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 1:6 1.2GHZ 24LFCSP 集成电路（IC） 时钟缓冲器，驱动器