丝印代码：AZ3683；ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features • Dual channel ADC • 18-bit 10, 25, 65 MSPS ADC • Noise floor: -160 dBFS/Hz • Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) • Latency: 1-2 clock cycles • 18-bit, no missing codes • INL/DNL: ±7/ ±0.7 LSB (typical) • Reference: external or intern

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features • Dual channel ADC • 18-bit 10, 25, 65 MSPS ADC • Noise floor: -160 dBFS/Hz • Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) • Latency: 1-2 clock cycles • 18-bit, no missing codes • INL/DNL: ±7/ ±0.7 LSB (typical) • Reference: external or intern

封装/外壳：40-WFQFN 裸露焊盘 包装：卷带（TR） 描述：IC ANALOG TO DIGITAL CONVERTER 集成电路（IC） 模数转换器（ADC）

丝印代码：AZ3683；ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：5.01183 Mbytes Page：75 Pages

丝印代码：AZ3683；ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：4.43597 Mbytes Page：73 Pages

丝印代码：AZ3683；ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：5.03782 Mbytes Page：75 Pages

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features • Dual channel ADC • 18-bit 10, 25, 65 MSPS ADC • Noise floor: -160 dBFS/Hz • Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) • Latency: 1-2 clock cycles • 18-bit, no missing codes • INL/DNL: ±7/ ±0.7 LSB (typical) • Reference: external or intern

Precision Potentiometer

文件：172.21 Kbytes Page：2 Pages

RAST-5-Steckverbinder, Raster 5,0 mm

文件：117.51 Kbytes Page：2 Pages

3680 Family - Precision Potentiometer

文件：178.77 Kbytes Page：2 Pages

Precision Potentiometer

文件：123.48 Kbytes Page：2 Pages

RAST 5 connectors, pitch 5.0 mm

文件：508.34 Kbytes Page：5 Pages