ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

文件：390.15 Kbytes Page：22 Pages

Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

文件：570.06 Kbytes Page：24 Pages

双通道、12 位、105MSPS、1.0GHz 输入带宽模数转换器 (ADC)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

1FEATURES 2• Internal Sample-and-Hold Circuit and Precision Reference • Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data Format • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)

Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

文件：570.06 Kbytes Page：24 Pages

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs

文件：343.36 Kbytes Page：14 Pages

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

封装/外壳：60-WFQFN 裸露焊盘 包装：管件 描述：IC ADC 12BIT PIPELINED 60WQFN 集成电路（IC） 模数转换器（ADC）

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

105 MSPS A/D Converter

文件：1.11656 Mbytes Page：26 Pages

包装：盒 描述：EVAL BOARD FOR ADC12DC105 开发板，套件，编程器 评估板 - 模数转换器（ADC）