Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes Page：44 Pages

封装/外壳：40-WFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK GEN PLL DUAL 40LFCSP 集成电路（IC） 应用特定时钟/定时

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes Page：44 Pages

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes Page：44 Pages

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes Page：44 Pages

封装/外壳：40-WFQFN 裸露焊盘，CSP 包装：托盘 描述：IC CLK GEN PLL DUAL 40LFCSP 集成电路（IC） 应用特定时钟/定时

MACHINE SCREW PAN PHILLIPS 10-32

文件：130.87 Kbytes Page：1 Pages