1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five indep

封装/外壳：48-VFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 2:5 1.2GHZ 48LFCSP 集成电路（IC） 时钟缓冲器，驱动器