型号 功能描述 生产厂家 企业 LOGO 操作
AD6620SSLASHPCB

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

AD6620SSLASHPCB

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

AD6620SSLASHPCB

67 MSPS Digital Receive Signal Processor

文件:399.31 Kbytes Page:44 Pages

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

AD

亚德诺

67 MSPS Digital Receive Signal Processor

文件:399.31 Kbytes Page:44 Pages

AD

亚德诺

更新时间:2025-9-26 10:07:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
恩XP
23+
NA
2500
全新原装假一赔十
AD
23+
QFP
3600
绝对全新原装!现货!特价!请放心订购!
ADI/亚德诺
23+
QFP128
50000
全新原装正品现货,支持订货
ADI(亚德诺)
23+
NA
20094
正纳10年以上分销经验原装进口正品做服务做口碑有支持
ADI/亚德诺
23+
BGA
5000
原厂授权代理,海外优势订货渠道。可提供大量库存,详
ADI
24+
原厂原装
539
原装房间现货!
AD
24+/25+
84
原装正品现货库存价优
ADI/亚德诺
23+
TO-59
8510
原装正品代理渠道价格优势
AD
25+
QFP80
3200
全新原装、诚信经营、公司现货销售!
AD
25+
4500
百分百原装正品 真实公司现货库存 本公司只做原装 可

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