低抖动时钟发生器

AC1571 是用于 5G 基站应用的基于 PLL 的时钟发生器，该芯片采用全数字锁相环技术，以实现最佳的高频低相噪性能，并具有低功耗和高 PSRR 能力。AC1571 使用 ADPLL 技术，可实现<0.3ps RMS 的相位抖动性能。\nAC1571 输出差分 100MHz，125MHz，156.25MHz 和单端 33.33MHz CPU 时钟，同时六个 LVCMOS 输出还用作 25MHz 晶振参考的驱动扇出。 • 七路单端LVCMOS输出，输出阻抗为30欧姆；\n• 1路单端LVCMOS（QD0）33.33MHz CPU时钟；\n• 晶体振荡器接口设计用于25MHz并联谐振晶体；\n• 125MHz下的RMS相位抖动，使用25MHz晶体（12kHz–20MHz）：0.27ps（典型）；\n• 3.3 v电源电压；\n• 无铅（RoHS 6）封装；;

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

DESCRIPTION The AIC1571 combines a synchronous voltage mode controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. One linear controller regul

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

DESCRIPTION The AIC1571 combines a synchronous voltage mode controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. One linear controller regul

Constant-Current/ Constant-Voltage Battery Charger with Preset Voltage and Termination Flag

文件：201.87 Kbytes Page：16 Pages

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

文件：434.05 Kbytes Page：29 Pages

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

文件：434.05 Kbytes Page：29 Pages