丝印代码：AB823；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB823；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB823；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

封装/外壳：模块 包装：盒 描述：821 MHZ CAVITY BAND PASS FILTER 滤波器 RF 滤波器

821 MHz Cavity Band Pass Filter

824 MHz Cavity Band Pass Filter

封装/外壳：模块，SMA 连接器 包装：托盘 描述：824 MHZ CAVITY BAND PASS FILTER 滤波器 RF 滤波器

829 MHz Cavity Band Pass Filter