丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bou

丝印代码：AB646A；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Typical VOLP (Output Ground Bounce)

丝印代码：AB646A；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Typical VOLP (Output Ground Bounce)

丝印代码：AB646A；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Typical VOLP (Output Ground Bounce)

丝印代码：AB646A；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Typical VOLP (Output Ground Bounce)

丝印代码：AB646A；OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Typical VOLP (Output Ground Bounce)

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：528.19 Kbytes Page：24 Pages

PNP SILICON POWER DARLINGTONS

PNP SILICON POWER DARLINGTONS ● Designed for Complementary Use with BD645, BD647, BD649 and BD651 ● 62.5 W at 25°C Case Temperature ● 8 A Continuous Collector Current ● Minimum hFE of 750 at 3 V , 3 A

HC648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV. HC646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE

DESCRIPTION The M74HC646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3- STATE) fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 73 MHz (TYP.) AT VCC = 5 V ■

Octal bus transceiver/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output c

PHASE CONTROL THYRISTOR

文件：44.27 Kbytes Page：4 Pages

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：175.07 Kbytes Page：10 Pages