Six Output Differential Buffer for PCIe Gen3

General Description: The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the inp

6-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectabl 6 - 0.7 V current mode differential HCSL output pairs\nCycle-to-cycle jitter < 50 ps\nOutput-to-output skew < 50 ps\nPCIe Gen3 phase jitter < 1.0 ps RMS\nOE# pins/Suitable for Express Card applications\nPLL or bypass mode/PLL can dejitter incoming clock\nSelectable PLL bandwidth/minimizes jitter pea;

SMBus Interface/unused outputs can be disabled

文件：199.65 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC CLK FANOUT/BUFF ZD 28SSOP 集成电路（IC） 应用特定时钟/定时

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：托盘 描述：IC CLK FANOUT/BUFF ZD 28SSOP 集成电路（IC） 应用特定时钟/定时

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen3

文件：238.69 Kbytes Page：14 Pages